By Singh L., Drucker L., Khann N.
"As chip dimension and complexity keeps to develop exponentially, the demanding situations of practical verification have gotten a severe factor within the electronics undefined. it's now normally heard that logical error neglected in the course of useful verification are the commonest reason for chip re-spins, and that the prices linked to sensible verification are actually outweighing the prices of chip layout. to deal with those demanding situations engineers are more and more counting on new layout and verification methodologies and languages. Transaction-based layout and verification, restricted random stimulus new release, sensible assurance research, and assertion-based verification are all options that complicated layout and verification groups generally use this present day. Engineers also are more and more turning to layout and verification types in response to C/C++ and SystemC so that it will construct extra summary, larger functionality and software program types and to flee the restrictions of RTL HDLs. This new ebook, complex Verification strategies: A SystemC dependent technique for winning Tapeout, offers particular suggestions for those complex verification suggestions, complex Verification recommendations: A SystemC established strategy for profitable Tapeout contains practical examples and exhibits how SystemC and SCV might be utilized to quite a few complicated layout and verification projects.
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Extra info for Advanced Verification Techniques: A Systemc Based Approach for Successful Tapeout
How powerful is debugger at handling multiple threads? Is the code structured and easily understandable? Is there additional software to worry about‚ additional training required etc.? Support components integration from different languages‚ in case IP is in a different language. Most of the verification languages try to provide the required capabilities listed above. Some are better than other in some cases. To explore more on what kind of features are provided with these HVLs‚ lets take an example of SCV.
Scripting language do the error checking at the last possible moment when value is being used. System languages can detect errors ar compile time. Generally system programming language is more code and less flexible programs compared to scripting language but they are highly efficient and can run at 10-20X faster since there are fewer run time checks. 32 Advanced Verification Techniques Applications can be developed much faster with scripting language but for complex algorithms and data structures, the strong typing of system programming language makes it more manageable.
Building own memory model: If there are enough resources available, you can spend time on building the memory model and use it for simulation. These can be build in any high level verification language or HDLs. Download freemodel: Memory vendors also provide free HDL models to download from. They might be highly accurate ones and available in Verilog or VHDLs from memory vendors for example Micron and Intel provide these. Buy commercial available models: Companies like Denali work with memory vendors to provide 100% accurate memory models for the components they manufacture.
Advanced Verification Techniques: A Systemc Based Approach for Successful Tapeout by Singh L., Drucker L., Khann N.